A process for dicing a semiconductor wafer having a plurality of integrated circuits has been suggested, which includes a step for forming a protective layer covering the integrated circuits of the semiconductor wafer, a step for patterning gaps on the protective layer to form a mask thereon, and a step for etching the semiconductor wafer through the gaps. For example, Patent Document 1 (JP 2015-519732 A or US 2013/267076 A1) suggests the step for patterning gaps on the protective layer by a multi-step laser scribing process with a laser beam having a Gaussian beam pass or a top hat beam pass.
Recently, a plasma etching process has been established as a process for dicing the substrate having a wiring layer and a semiconductor layer into a plurality of element chips, in which a plurality of groove-like apertures (gaps, which may also be referred as streets) are formed in dicing regions of wiring layers, and the semiconductor layer is etched along the apertures by the plasma exposure onto the semiconductor layer uncovered by the protective layer. When laser-scribing the dicing regions with the Gaussian beam pass or the top hat beam pass as proposed by Patent Document 1, the semiconductor layer is damaged on bottom surfaces around a center of the apertures, a material of the wiring layer is melted, and the melted material is trapped and re-solidified in damaged portions on the surfaces of the semiconductor layer. On the other hand, when laser-scribing the dicing regions with the laser beam having reduced intensity, the energy density at peripheral portions of the laser beam is insufficient such that side walls to be formed along both sides of the wiring layer have tapered angle less than the expected one, resulting in insufficient verticality of the side walls.